This invention relates to field effect transistors (FETs) formed in complimentary metal oxide semiconductor (CMOS) integrated circuits (ICs). More particularly, the present invention relates to a new and improved planar FET having a short-length and vertically-oriented channel structure interdigitated with a dual-gate structure to obtain fully-depleted and fully-inverted channel operating and conductivity characteristics. Moreover, the present invention relates to fabricating such an improved FET using conventional CMOS fabrication techniques, including photolithographic techniques which are incapable themselves of achieving structural widths as small as required for the FET to obtain the fully-depleted and fully-inverted channel operating and conductivity characteristics.
During the two decades preceding this invention, the continual evolution of semiconductor technology has seen the size or topology of transistors shrink by about half at regular time intervals of approximately 18 months. As a result, the density of FETs in comparably-sized ICs has doubled that the same rate. It is predicted that this doubling effect will reach a point where physics and economics can no longer support such increases in density, and may reach proportions where no further density increases will be possible by using the presently-preferred, conventional planar CMOS fabrication techniques.
Conventional CMOS FETs are typically formed in a structural configuration referred to as xe2x80x9cplanarxe2x80x9d because the various regions of the FET are formed in patterns established in a horizontal plane. For example, the source and drain regions are formed as horizontal planar structures extending downward into a substrate from an upper horizontal surface. Similarly, the channel structure of the FET, which extends between the source and drain regions, is also formed as a horizontal planar structure. The gate structure extends as a generally planar layer of material formed on top of the channel structure. Although all of these regions and components have a vertical dimension, the majority of their influence in the FET is achieved because of the horizontal extent of their regions and structures. The typical CMOS fabrication technique utilizes these planar configurations because they are easily fabricated in a horizontal plane using conventional techniques which are directed vertically downward onto the substrate or other structures formed on top of the substrate.
The planar aspects of the conventional CMOS structures have been recognized as a significant limitation on the continually diminishing size evolution in CMOS FETs. For example, as the size of the source, drain, channel and gate regions are reduced in the horizontal plane, the length of the channel becomes shorter, placing the source and drain regions in closer proximity with one another. This closer proximity diminishes the ability of the gate structure to control conductivity through the channel, and hence the conductivity of the FET itself. These adverse influences on the conductivity characteristics of the FET are referred to as short channel effects.
Short channel effects are explained as follows. Conductivity through the channel is controlled by a vertical electric field created by the gate voltage in a direction perpendicular to the flow of current in the channel. However, an electric field is also created by the charged source and drain regions. The source and drain fields encroach laterally onto the channel. As the channel length shortens, the lateral drain and source fields have a greater influence on the channel conductivity characteristics. With a sufficiently short channel, the lateral source and drain fields can cause the gate field to lose control over the FET conductivity, even to the extent of creating a short between the source and the drain, thus diminishing or destroying the operating characteristics of the FET.
Shrinking the size of the FET structure also requires reducing the size of the gate oxide and source and drain regions, thus creating the requirement that the power supply voltage must also be reduced to maintain gate oxide integrity and junction breakdown margins to prevent wear out due to voltage stress and diminished lifetime resulting from hot carrier injection. Reducing the voltage of the power supply creates semiconductor package and circuit board-level design problems to accommodate multiple different power supply voltage levels. Such requirements increase the cost of semiconductor fabrication as well as future costs of developing technology.
FET structures which are alternatives to planar structures have been conceived as partial solutions to the diminishing size problems. One such structure is a dual-gate structure. In general, a dual-gate structure involves placing a gate on opposite sides of the channel. Because both sides of the channel are thereby subjected to the gate field, rather than the single side of the channel in a conventional planar FET structure, the gate will maintain a predominant field affect over the lateral fields from the source and drain even when the length of the channel is reduced. The difficulty with dual-gate FET structures is that they are very difficult to manufacture. The manufacturing difficulties have prevented dual-gate FETs from achieving a significant level of commercial acceptability.
One type of dual-gate FET involves a xe2x80x9cgate-all-aroundxe2x80x9d configuration. The gate-all-around configuration is created by forming a cavity beneath a silicon channel structure by an isotropic etch. After gate oxidation, the cavity under the channel silicon structure is under-filled by polysilicon which is deposited by chemical vapor deposition. Thereafter, gate material is placed over the top of the channel silicon structure and in contact with the under-filled material in the cavity. The resulting gate structure completely surrounds the silicon channel structure, thereby causing the gate to completely encircle the channel. Ends of the channel structure become the source and drain. The gate-all-around fabrication process is very complex and difficult to execute on a reliable and consistent basis.
Another method of forming a gate-all-around MOSFET structure provides for forming a tunnel of the gate material. The source, channel and drain are then created by epitaxially growing silicon through the preformed tunnel.
Another type of a dual-gate FET is called a xe2x80x9cdeltaxe2x80x9d configuration. The delta configuration involves forming a generally rectangular wall of silicon which extends vertically upward from the substrate, positioning the rectangular wall on a narrow edge. The vertical extension of the wall is usually formed by eroding or otherwise eliminating areas of the substrate adjacent to the junction of the vertically-extending wall with the substrate. Gate material is thereafter deposited over the sides and top of the wall. A field oxidation process may cause the field oxide to penetrate the bulk silicon at the base of the junction of the wall with the substrate until the field oxide on both sides of the wall junction meet, thereby xe2x80x9cpinching offxe2x80x9d the channel from the bulk silicon. The gate material surrounds the wall on at least three sides, thereby establishing a gate electric field over most of the silicon structure which forms the channel. Ends of the silicon wall structure which extend out beyond the gate material become the source and drain regions for the FET.
Another type of structure that is similar to the gate-all-around MOSFET is called the xe2x80x9csurrounding-gatexe2x80x9d MOSFET. A vertical pillar of silicon is surrounded or wrapped by the gate material. The base of the silicon pillar is connected to the substrate, or a structure formed on the substrate, and forms the source. The top of the pillar protrudes out of the surrounding gate material and forms the drain. The pillar of a surrounding-gate MOSFET may be cylindrically or elongated rectangularly shaped in a top view cross section. Fabrication processes may cause the short edges of a rectangular pillar to be rounded. The cylindrical pillar configuration is essentially a special case of the rectangular configuration in which all the edges are short and the device fabrication processes cause the entire pillar to be rounded. These devices are asymmetrical since the source and the drain are not similar, as is the case in many horizontal configurations. Additionally, fabrication of these devices must utilize non-planar techniques.
Both the gate-all-around and the delta FET structures are typically formed using silicon-on-insulator (SOI) technology. SOI technology involves forming the FET structures on an insulating layer. Isolating the FET structure from the substrate by the insulating layer is believed to enhance short channel behavior because the transistor is less susceptible to breakdown and leakage currents and because of a general increase in performance as a result of a diminished capacitance with the substrate. However, SOI FETs are more susceptible to undesirable snapback and parasitic surface transistor effects because of the isolation of the source, drain and channel structure from the substrate.
Short channel FETs are also fabricated on epitaxial substrates, which are more expensive than bulk substrates. Some dual-gate FET structures also require that the material of certain components be grown epitaxially during the fabrication of the transistor. The epitaxial growth of components during transistor fabrication is time-consuming and expensive.
The gate-all-around, surrounding-gate and delta FET structures are difficult to construct on a consistent, reliable basis. Furthermore, SOI and epitaxial structures are also expensive. The surrounding-gate structures require pillars that are tall and difficult to construct. Moreover, all previously known processes for fabricating dual-gate FETs are very complex, and require steps and procedures which are considerably more complex and difficult to execute than conventional CMOS fabrication techniques. As a consequence, the previously-known dual-gate FET structures are not economically feasible to fabricate on a commercial, large-volume basis at the present time.
It is with respect to these and other background considerations that the present invention has evolved.
In its most general sense, the present invention relates to a method of fabricating a field effect transistor (FET) which comprises the steps of forming a plurality of channel segments in a starting material, with the channel segments extending longitudinally between source and drain areas. The channel segments are laterally separated from one another by spaces. The channel segments are preferably formed from pillars of starting material located between the spaces, and the pillars are laterally oxidized from within the spaces. The lateral oxidation is removed to reduce the width of the pillars and form the channel segments. A gate structure is formed in the spaces between the channel segments. Preferably, a bridge structure extends over the channel segments and connects to the upper ends of gate segments between the channel segments.
A reduced aspect ratio FET having a dual gate structure and a short-length and preferably vertically-oriented channel structure is obtained, and the resulting FET is substantially immune to or resistant to adverse short channel effects. The FET may be fabricated using conventional CMOS fabrication steps, augmented only by the additional step of subtractive oxidation to create the channel structure.
Additional preferable steps employed in forming the channel segments from the pillars include forming an etch-resistant barrier, preferably photoresist material or film stack, on top of the starting material at the location of each pillar, and etching the spaces into the starting material between each of the etch-resistant barriers on top of each pillar after photolithographically exposing and developing the layer of photoresist material. The width of the etch-resistant barrier is made as narrow as possible by photolithographic exposure. The subtractive oxidation of the pillars laterally reduces their width to create the channel segments which have a width substantially less than the width of the etch resistant barrier and which is less than that which can be obtained from contemporary conventional photolithographic patterning techniques. However, conventional CMOS photolithographic patterning techniques and subtractive oxidation are used to create the channel segments.
The relatively narrow channel widths allow fully-depleted or fully-inverted conductivity characteristics which enhance the performance of the FET despite its reduced size. The fully-depleted and fully-inverted conductivity characteristics are obtained from a bulk substrate without the need for a SOI or epitaxial substrate or the epitaxial growth of structures within the FET structure.
Further improvements in the formation of the channel segments are obtained by the preferable steps of oxidizing the pillars laterally with the etch-resistant barrier and an oxidation-resistant cap (preferably silicon nitride) remaining on top of the pillars, preferably while laterally etching the etch-resistant barrier to reduce the width of the barrier and to expose upper corners of the pillar material to erosion when etching the spaces. An oxide cap layer may also be formed between the oxidation-resistant cap and an upper end of each pillar. The laterally outer side walls of the pillars are oxidized to a desired thickness, such that the oxidized portion grows in thickness. The upper end of each pillar, directly under the oxide cap layer, is also grown in thickness at laterally outer locations adjacent to the side walls of the pillars, and this growth results in oxidizing the upper lateral outside corners of the pillar material in a rounded corner configuration or upper rounded ends, or longitudinally-extending edges on the channel segments. The oxide cap layer protects the center of the upper end of the pillars against oxidation during lateral oxidation of the pillars. The upper rounded ends or curved edges prevent carrier tunneling from the gate to the bulk of the FET structure, thereby avoiding gate oxide breakdown and diminished gate oxide integrity. The improved gate field characteristics also result in greater immunity from hot electron impact on the gate and prolong useful longevity of the FET.
Further preferable improvements in the fabrication steps involve implanting a layer of material into the upper end of each channel segment, and implanting a layer of material into the starting material beneath each space. The implanted layers turn off any parasitic surface transistor at those locations, thereby further enhancing the performance of the FET.
The dual-gate structure is formed on opposite sides of the narrow channel structures using conventional self-aligning CMOS material deposition techniques to create the gate structure, preferably from in situ doped polysilicon. Each channel segment has a lateral width which is substantially less than a lateral width of each gate segment, to accommodate the self-aligning deposition. A variety of other conventional CMOS techniques may be retained in fabricating the small aspect ratio FET, such as forming the gate structure with a plurality of generally vertically oriented gate segments positioned between the vertically oriented channel segments, forming the channel segments in a generally rectangularly shaped configuration, forming the channel segments in a generally parallel aligned relationship with one another, forming the starting material by forming a well in a substrate material, forming the source and drain areas generally in a planar configuration, and implanting the source and drain areas into the starting material. Despite the shorter channel length, an enhanced source-drain breakdown voltage characteristic is obtained because the source and drain regions may be implanted to greater depths. An enhanced tolerance for, or an increased capability to withstand, higher supply voltages is obtained because of the ability to increase the thickness of the gate oxide while still reducing the size of the components within the FET to achieve a smaller overall aspect ratio.
The FET structure may be fabricated on bulk substrate, avoiding the added costs associated with epitaxial or SOI substrate processing. The configuration of the dual-gate and channel structures avoids parasitic and snapback problems common to S0I structures. In general, the FET structure of the present invention may be fabricated on a reliable, economic, large-scale commercial basis, despite size reduction.
A more complete appreciation of the present invention and its scope, and the manner in which it achieves the above noted improvements, can be obtained by reference to the following detailed description of presently preferred embodiments of the invention taken in connection with the accompanying drawings, which are briefly summarized below, and the appended claims.